The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 26, 2016
Filed:
Feb. 12, 2014
International Business Machines Corporation, Armonk, NY (US);
Kabushiki Kaisha Toshiba, Tokyo, JP;
Veeraraghavan S. Basker, Schenectady, NY (US);
Akira Hokazono, Kawasaki, JP;
Hiroshi Itokawa, Kuwana, JP;
Tenko Yamashita, Schenectady, NY (US);
Chun-chen Yeh, Clifton Park, NY (US);
International Business Machines Corporation, Armonk, NY (US);
KABUSHIKI KAISHA TOSHIBA, Tokyo, JP;
Abstract
Effective transfer of stress to a channel of a fin field effect transistor is provided by forming stress-generating active semiconductor regions that function as a source region and a drain region on a top surface of a single crystalline semiconductor layer. A dielectric material layer is formed on a top surface of the semiconductor layer between semiconductor fins. A gate structure is formed across the semiconductor fins, and the dielectric material layer is patterned employing the gate structure as an etch mask. A gate spacer is formed around the gate stack, and physically exposed portions of the semiconductor fins are removed by an etch. Stress-generating active semiconductor regions are formed by selective epitaxy from physically exposed top surfaces of the semiconductor layer, and apply stress to remaining portions of the semiconductor fins that include channels.