The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 26, 2016

Filed:

Mar. 17, 2014
Applicant:

Silicon Storage Technology, Inc., San Jose, CA (US);

Inventors:

Nhan Do, Saratoga, CA (US);

Elizabeth A. Cuevas, Los Gatos, CA (US);

Yuri Tkachev, Sunnyvale, CA (US);

Mandana Tadayoni, Cupertino, CA (US);

Henry A. Om'mani, Santa Clara, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 16/26 (2006.01); H01L 27/115 (2006.01); G11C 16/14 (2006.01);
U.S. Cl.
CPC ...
G11C 16/26 (2013.01); G11C 16/0433 (2013.01); G11C 16/14 (2013.01); H01L 27/115 (2013.01);
Abstract

A method of operating a memory cell that comprises first and second regions spaced apart in a substrate with a channel region therebetween, a floating gate disposed over the channel region and the fir region, a control gate disposed over the channel region and laterally adjacent to the floating gate with a portion disposed over the floating gate, and a coupling gate disposed over the first region and laterally adjacent to the floating gate. A method of erasing the memory cell includes applying a positive voltage to the control gate and a negative voltage to the coupling gate. A method of reading the memory cell includes applying positive voltages to the control gate, to the coupling gate, and to one of the first and second regions.


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