The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 19, 2016

Filed:

Dec. 27, 2011
Applicants:

Lawrence D. Wong, Beaverton, OR (US);

Scott B. Clendenning, Portland, OR (US);

David J. Michalak, Portland, OR (US);

Inventors:

Lawrence D. Wong, Beaverton, OR (US);

Scott B. Clendenning, Portland, OR (US);

David J. Michalak, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 51/05 (2006.01); H01L 29/40 (2006.01); H01L 51/00 (2006.01); H01L 21/84 (2006.01); H01L 27/12 (2006.01); B82B 3/00 (2006.01);
U.S. Cl.
CPC ...
H01L 51/0048 (2013.01); B82B 3/0047 (2013.01); H01L 21/845 (2013.01); H01L 27/1211 (2013.01); H01L 51/0002 (2013.01); H01L 51/0558 (2013.01);
Abstract

Embodiments of the invention provide transistor structures and interconnect structures that employ carbon nanotubes (CNTs). Further embodiments of the invention provide methods of fabricating transistor structures and interconnect structures that employ carbon nanotubes. Deterministic nanofabrication techniques according to embodiments of the invention can provide efficient routes for the large-scale manufacture of transistor and interconnect structures for use, for example, in random logic and memory circuit applications.


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