The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 19, 2016

Filed:

Aug. 04, 2014
Applicants:

Stmicroelectronics SA, Montrouge, FR;

Stmicroelectronics, Inc., Coppell, TX (US);

Inventors:

Pierre Morin, Albany, NY (US);

Denis Rideau, Grenoble, FR;

Olivier Nier, Varces, FR;

Assignees:

STMicroelectronics SA, Montrouge, FR;

STMicroelectronics, Inc., Coppell, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/324 (2006.01); H01L 21/762 (2006.01); H01L 29/78 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66772 (2013.01); H01L 21/0217 (2013.01); H01L 21/324 (2013.01); H01L 21/76283 (2013.01); H01L 27/1211 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/7843 (2013.01); H01L 29/7847 (2013.01);
Abstract

The disclosure concerns a method of stressing a semiconductor layer comprising: forming, over a silicon on insulator structure having a semiconductor layer in contact with an insulating layer, one or more stressor blocks aligned with first regions of said semiconductor layer in which transistor channels are to be formed, wherein said stressor blocks are stressed such that they locally stress said semiconductor layer; and deforming second regions of said insulating layer adjacent to said first regions by temporally decreasing, by annealing, the viscosity of said insulator layer.


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