The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 19, 2016

Filed:

Aug. 22, 2014
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventor:

Hsueh-An Yang, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); B81C 1/00 (2006.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01); H01L 21/76 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76885 (2013.01); B81C 1/0023 (2013.01); B81C 1/00238 (2013.01); B81C 1/00571 (2013.01); H01L 21/76 (2013.01); H01L 21/76898 (2013.01); H01L 23/3171 (2013.01); H01L 23/481 (2013.01); B81C 2203/0771 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05 (2013.01); H01L 2224/05569 (2013.01); H01L 2224/13 (2013.01); H01L 2224/13022 (2013.01); H01L 2924/0002 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/1461 (2013.01);
Abstract

A method of forming a semiconductor device package includes bonding a front surface of a first substrate to a second substrate, and thinning a back surface of the first substrate. The method includes depositing and patterning a dielectric layer on the thinned back surface of the first substrate, and etching the first substrate after the depositing and the patterning of the dielectric layer are performed to form a through silicon via to enable electrical connection with a first level metal of the first substrate. The method includes depositing an isolation layer to line the through silicon via is formed, and etching the isolation layer at the bottom of the through silicon via. The method includes depositing a conductive layer to line the through silicon via after the isolation layer at the bottom of the through silicon via is etched, and deposited a copper film over the conductive layer.


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