The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 12, 2016

Filed:

Apr. 16, 2014
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Sanjeev Jahagirdar, Folsom, CA (US);

Varghese George, Folsom, CA (US);

John B. Conrad, Folsom, CA (US);

Robert Milstrey, Citrus Heights, CA (US);

Stephen A. Fischer, Gold River, CA (US);

Alon Naveh, Ramat Hasharon, IL;

Shai Rotem, Haifa, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2006.01); G06F 12/08 (2006.01); G06F 11/14 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3287 (2013.01); G06F 1/3203 (2013.01); G06F 1/3243 (2013.01); G06F 1/3246 (2013.01); G06F 1/3275 (2013.01); G06F 1/3296 (2013.01); G06F 11/1441 (2013.01); G06F 12/084 (2013.01); G06F 12/0875 (2013.01); G11C 7/1072 (2013.01); G06F 2212/281 (2013.01); G06F 2212/305 (2013.01); Y02B 60/1239 (2013.01); Y02B 60/1285 (2013.01); Y02B 60/32 (2013.01); Y10T 307/305 (2015.04); Y10T 307/406 (2015.04); Y10T 307/582 (2015.04); Y10T 307/826 (2015.04);
Abstract

Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.


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