The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 2016

Filed:

Jan. 28, 2015
Applicant:

Sandisk Technologies Inc., Plano, TX (US);

Inventors:

Donovan Lee, Santa Clara, CA (US);

Vinod Purayath, Santa Clara, CA (US);

James Kai, Santa Clara, CA (US);

George Matamis, Danville, CA (US);

Assignee:

SANDISK TECHNOLOGIES INC., Plano, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 27/115 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11521 (2013.01); H01L 21/28273 (2013.01); H01L 27/11517 (2013.01); H01L 27/11524 (2013.01); H01L 29/42324 (2013.01); H01L 29/42328 (2013.01);
Abstract

A method of making a NAND string includes forming a tunnel dielectric over a semiconductor channel, forming a charge storage layer over the tunnel dielectric, forming a blocking dielectric over the charge storage layer, and forming a control gate layer over the blocking dielectric. The method also includes patterning the control gate layer to form a plurality of control gates separated by trenches, and reacting a first material with exposed sidewalls of the plurality of control gates to form self aligned metal-first material compound sidewall spacers on the exposed sidewalls of the plurality of control gates.


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