The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 2016

Filed:

May. 16, 2014
Applicant:

United Microelectronics Corp., Hsinchu, TW;

Inventors:

Hsin-Kuo Hsu, Kaohsiung, TW;

Li-Chieh Hsu, Taichung, TW;

Hsiang-Hao Chen, New Taipei, TW;

Chung-Wei Hsueh, Kaohsiung, TW;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/311 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 21/768 (2006.01); H01L 21/3213 (2006.01); H01L 21/321 (2006.01);
U.S. Cl.
CPC ...
H01L 23/528 (2013.01); H01L 21/3212 (2013.01); H01L 21/32134 (2013.01); H01L 21/7684 (2013.01); H01L 21/7685 (2013.01); H01L 21/76843 (2013.01); H01L 21/76877 (2013.01); H01L 23/53238 (2013.01);
Abstract

A method for manufacturing a semiconductor device and a device manufactured using the same are provided. According to the embodiment, substrate with a dielectric layer formed thereon is provided. Plural trenches are defined in the dielectric layer, and the trenches are isolated by the dielectric layer. A first barrier layer is formed in the trenches as barrier liners of the trenches, followed by filling the trenches with a conductor. Then, the conductor in the trenches is partially removed to form a plurality of recesses, wherein remained conductor has a flat surface. Next, a second barrier layer is formed in the recesses as barrier caps of the trenches.


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