The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 2016

Filed:

Feb. 24, 2015
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Ching-Wen Hung, Tainan, TW;

Jia-Rong Wu, Kaohsiung, TW;

Chih-Sen Huang, Tainan, TW;

Yi-Wei Chen, Taichung, TW;

Chia Chang Hsu, Kaohsiung, TW;

Assignee:

UNITED MICROELECTRONICS CORP., Science-Based Industrial Park, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/285 (2006.01); H01L 29/66 (2006.01); H01L 21/324 (2006.01); H01L 21/308 (2006.01); H01L 21/28 (2006.01); H01L 21/3205 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28518 (2013.01); H01L 21/28052 (2013.01); H01L 21/3081 (2013.01); H01L 21/324 (2013.01); H01L 21/32053 (2013.01); H01L 29/665 (2013.01);
Abstract

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon and an interlayer dielectric (ILD) layer around the gate structure; forming a dielectric layer on the gate structure and the ILD layer; forming a patterned hard mask on the dielectric layer; forming an opening in the dielectric layer and the ILD layer; performing a silicide process for forming a silicide layer in the opening; removing the patterned hard mask and un-reacted metal after the silicide process; and forming a contact plug in the opening.


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