The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 05, 2016
Filed:
Dec. 20, 2013
Pascal A. Meinerzhagen, Lausanne, CH;
Jaydeep P. Kulkarni, Portland, OR (US);
Muhammad M. Khellah, Tigard, OR (US);
Cyrille Dray, Hillsboro, OR (US);
Dinesh Somasekhar, Portland, OR (US);
James W. Tschanz, Portland, OR (US);
Vivek K. DE, Beaverton, OR (US);
Pascal A. Meinerzhagen, Lausanne, CH;
Jaydeep P. Kulkarni, Portland, OR (US);
Muhammad M. Khellah, Tigard, OR (US);
Cyrille Dray, Hillsboro, OR (US);
Dinesh Somasekhar, Portland, OR (US);
James W. Tschanz, Portland, OR (US);
Vivek K. De, Beaverton, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Described is an apparatus which comprises: a first power supply node to provide a first power supply, a second power supply node, and a third power supply node; a first transistor which is operable to couple the first and second power supply nodes; and a charge pump circuit to provide a boosted voltage to the third power supply node in one mode, and to recover charge from the second power node in another mode. Described is a memory unit which comprises: a DRAM which is operable to be refreshed; a gated power supply node coupled to the DRAM to provide a gated power supply to the DRAM; and a charge recycling circuit to recover charge from the gated power supply node after the DRAM is refreshed.