The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 2016

Filed:

Feb. 23, 2013
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Edward S. Peterson, Rio Rancho, NM (US);

Roger D. Flateau, Jr., San Jose, CA (US);

James D. Wesselkamper, Albuquerque, NM (US);

Steven E. McNeil, Rio Rancho, NM (US);

Jason J. Moore, Albuquerque, NM (US);

Lester S. Sanders, Albuquerque, NM (US);

Lawrence C. Hung, San Jose, CA (US);

Yatharth K. Kochar, Hyderabad, IN;

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/00 (2006.01); G06F 15/177 (2006.01); G06F 21/57 (2013.01); G06F 9/44 (2006.01); G06F 21/76 (2013.01);
U.S. Cl.
CPC ...
G06F 21/575 (2013.01); G06F 9/4401 (2013.01); G06F 9/4406 (2013.01); G06F 9/4416 (2013.01); G06F 21/76 (2013.01);
Abstract

A system generally relating to an SoC, which may be a field programmable SoC ('FPSoC'), is disclosed. In this SoC, dedicated hardware includes a processing unit, a first internal memory, a second internal memory, an authentication engine, and a decryption engine. A storage device is coupled to the SoC. The storage device has access to a boot image. The first internal memory has boot code stored therein. The boot code is for a secure boot of the SoC. The boot code is configured to cause the processing unit to control the secure boot.


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