The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 2015

Filed:

Apr. 10, 2014
Applicant:

Siltronic Ag, Munich, DE;

Inventors:

Rainer Baumann, Burghausen, DE;

Johannes Staudhammer, Burghausen, DE;

Alexander Heilmaier, Haiming, DE;

Leszek Mistur, Burghausen, DE;

Klaus Roettger, Bachmehring, DE;

Assignee:

SILTRONIC AG, Munich, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B24B 37/08 (2012.01); H01L 21/304 (2006.01); B24B 53/017 (2012.01);
U.S. Cl.
CPC ...
B24B 37/08 (2013.01); B24B 53/017 (2013.01); H01L 21/304 (2013.01);
Abstract

A method of polishing a semiconductor wafer includes simultaneous double-side polishing the wafer in a gap of a polishing device between a lower polishing plate covered with a lower polishing pad and upper polishing plate covered with an upper polishing pad while supplying a polishing agent. A first of the upper and lower polishing pads is dressed using a dressing tool. The dressing tool is mounted in the gap so that it extends from the inner edge to the outer edge of the first polishing pad. The distance between the dressing tool and a second of the upper and lower polishing pads at the inner edge of the second polishing pad differs from a corresponding distance at the outer edge of the second polishing pad. After the dressing, the at least one semiconductor wafer in the gap is polished.


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