The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 22, 2015

Filed:

Dec. 19, 2013
Applicants:

Jacob T. Williams, Austin, TX (US);

Cheong Min Hong, Austin, TX (US);

Sung-taeg Kang, Austin, TX (US);

David G. Kolar, Austin, TX (US);

Jane A. Yater, Austin, TX (US);

Inventors:

Jacob T. Williams, Austin, TX (US);

Cheong Min Hong, Austin, TX (US);

Sung-Taeg Kang, Austin, TX (US);

David G. Kolar, Austin, TX (US);

Jane A. Yater, Austin, TX (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01); H01L 29/792 (2006.01); H01L 21/3213 (2006.01); H01L 21/3105 (2006.01); H01L 21/321 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 29/792 (2013.01); H01L 21/28282 (2013.01); H01L 21/31055 (2013.01); H01L 21/3212 (2013.01); H01L 21/32133 (2013.01); H01L 21/32139 (2013.01); H01L 29/42332 (2013.01); H01L 29/42344 (2013.01); H01L 29/66825 (2013.01); H01L 29/66833 (2013.01); H01L 29/7881 (2013.01);
Abstract

A method of forming a flash memory cell includes forming a first hard mask and a second hard mask on a substrate. A select gate is formed as a spacer around the first hard mask. A charge storage layer is formed over the first and second hard masks and the select gate. A control gate is formed as a spacer around the second hard mask. A recess in the control gate is filled with a dielectric material. The recess is formed between a curved sidewall of the control gate and a sidewall of the charge storage layer directly adjacent the curved sidewall of the control gate.


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