The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 22, 2015

Filed:

Nov. 11, 2011
Applicants:

Chih-ping Lin, Taipei County, TW;

Pi-kuang Chuang, Taichung, TW;

Hung-li Chang, Hsinchu County, TW;

Shih-ming Chen, Hsinchu, TW;

Hsiao-ying Yang, Hsinchu, TW;

Inventors:

Chih-Ping Lin, Taipei County, TW;

Pi-Kuang Chuang, Taichung, TW;

Hung-Li Chang, Hsinchu County, TW;

Shih-Ming Chen, Hsinchu, TW;

Hsiao-Ying Yang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/00 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823481 (2013.01); H01L 21/823412 (2013.01); H01L 21/823493 (2013.01); H01L 21/823807 (2013.01); H01L 21/823878 (2013.01); H01L 21/823892 (2013.01);
Abstract

A method for fabricating a semiconductor device is provided. A substrate comprising a P-well is provided. A low voltage device area and a high voltage device area are defined in the P-well. A photoresist layer is formed on the substrate. A photomask comprising a shielding region is provided. The shielding region is corresponded to the high voltage device area. A pattern of the photomask is transferred to the photoresist layer on the substrate by a photolithography process using the photomask. A P-type ion field is formed outside of the high-voltage device area by selectively doping P-type ions into the substrate using the photoresist layer as a mask.


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