The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 22, 2015

Filed:

Jan. 28, 2014
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Saravjeet Singh, Santa Clara, CA (US);

Brad Eaton, Menlo Park, CA (US);

Ajay Kumar, Cupertino, CA (US);

Wei-Sheng Lei, San Jose, CA (US);

James M. Holden, San Jose, CA (US);

Madhava Rao Yalamanchili, Morgan Hill, CA (US);

Todd J. Egan, Fremont, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/67 (2006.01); H01L 21/78 (2006.01); H01L 21/3065 (2006.01); H01L 21/308 (2006.01); H01L 21/683 (2006.01); H01L 21/687 (2006.01); B23K 26/06 (2014.01); B23K 26/36 (2014.01); B23K 26/40 (2014.01);
U.S. Cl.
CPC ...
H01L 21/67069 (2013.01); B23K 26/0635 (2013.01); B23K 26/367 (2013.01); B23K 26/409 (2013.01); B23K 26/4075 (2013.01); H01L 21/3065 (2013.01); H01L 21/3081 (2013.01); H01L 21/67092 (2013.01); H01L 21/67207 (2013.01); H01L 21/6836 (2013.01); H01L 21/68707 (2013.01); H01L 21/78 (2013.01); H01L 2221/68327 (2013.01); H01L 2221/68377 (2013.01);
Abstract

Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The semiconductor wafer is supported by a substrate carrier. The mask is then patterned with a laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits while supported by the substrate carrier.


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