The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 15, 2015

Filed:

May. 21, 2012
Applicants:

Mukta G. Farooq, Hopewell Junction, NY (US);

Troy L. Graves-abe, Wappingers Falls, NY (US);

Spyridon Skordas, Troy, NY (US);

Kevin R. Winstel, East Greenbush, NY (US);

Inventors:

Mukta G. Farooq, Hopewell Junction, NY (US);

Troy L. Graves-Abe, Wappingers Falls, NY (US);

Spyridon Skordas, Troy, NY (US);

Kevin R. Winstel, East Greenbush, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 25/065 (2006.01); H01L 23/538 (2006.01); H01L 27/06 (2006.01);
U.S. Cl.
CPC ...
H01L 24/09 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 23/5386 (2013.01); H01L 25/0657 (2013.01); H01L 27/0688 (2013.01); H01L 2224/02205 (2013.01); H01L 2224/0905 (2013.01); H01L 2225/06544 (2013.01); H01L 2924/0002 (2013.01); H01L 2924/14 (2013.01); H01L 2924/3701 (2013.01);
Abstract

Circuits incorporating three-dimensional integration and methods of their fabrication are disclosed. One circuit includes a bottom layer and a plurality of upper layers. The bottom layer includes a bottom landing pad connected to functional components in the bottom layer. In addition, the upper layers are stacked above the bottom layer. Each of the upper layers includes a respective upper landing pad that is connected to respective functional components in the respective upper layer. The landing pads are coupled by a single conductive via and are aligned in a stack of the bottom layer and the upper layers such that each of the landing pads is offset from any of the landing pads in an adjacent layer in the stack by at least one pre-determined amount.


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