The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 15, 2015
Filed:
May. 21, 2013
Applicant:
Xilinx, Inc., San Jose, CA (US);
Inventors:
Qi Xiang, San Jose, CA (US);
Xiao-Yu Li, San Jose, CA (US);
Cinti X. Chen, San Jose, CA (US);
Glenn O'Rourke, Gilroy, CA (US);
Assignee:
XILINX, INC., San Jose, CA (US);
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/552 (2006.01); H01L 23/60 (2006.01); H01L 21/82 (2006.01); H01L 25/065 (2006.01); H01L 25/07 (2006.01); H01L 25/18 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/60 (2013.01); H01L 21/82 (2013.01); H01L 24/73 (2013.01); H01L 25/0652 (2013.01); H01L 25/0655 (2013.01); H01L 25/071 (2013.01); H01L 25/072 (2013.01); H01L 25/18 (2013.01);
Abstract
An apparatus relating generally to an interposer is disclosed. In such an apparatus, the interposer has a plurality of conductors and a plurality of charge attracting structures. The plurality of charge attracting structures are to protect at least one integrated circuit die to be coupled to the interposer to provide a stacked die. The plurality of conductors include a plurality of through-substrate vias.