The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 15, 2015

Filed:

Feb. 17, 2014
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Marie Denison, Plano, TX (US);

Brian Ashley Carpenter, Cary, NC (US);

Osvaldo Jorge Lopez, Annandale, NJ (US);

Juan Alejandro Herbsommer, Allen, TX (US);

Jonathan Noquil, Bethlehem, PA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49524 (2013.01); H01L 23/49562 (2013.01); H01L 23/49575 (2013.01); H01L 24/34 (2013.01); H01L 23/49838 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48137 (2013.01); H01L 2224/48247 (2013.01); H01L 2924/1301 (2013.01); H01L 2924/1305 (2013.01); H01L 2924/1306 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/15747 (2013.01);
Abstract

A packaged multi-output converter () comprising a leadframe with a chip pad () as ground terminal and a plurality of leads () including the electrical input terminal (); a first FET chip (sync chip,) with its source terminal affixed to the leadframe and on its opposite surface a first drain terminal () positioned adjacent to a second drain terminal (), the drain terminals connected respectively by a first () and a second () metal clip to a first () and second () output lead; a second FET chip (control chip,), positioned vertically over the first drain terminal, with its source terminal attached onto the first clip; a third FET chip (control chip,), positioned vertically over the second drain terminal, with its source terminal attached onto the second clip; and the drain terminals () of the second and third chips attached onto a third metal clip () connected to the input lead ().


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