The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 15, 2015

Filed:

Oct. 06, 2014
Applicants:

Jae-hwa Park, Yongin-si, KR;

Kwang-jin Moon, Hwaseong-si, KR;

Suk-chul Bang, Yongin-si, KR;

Byung-iyul Park, Seoul, KR;

Jeong-gi Jin, Osan-si, KR;

Tae-seong Kim, Suwon-si, KR;

Sung-hee Kang, Seongnam-si, KR;

Inventors:

Jae-Hwa Park, Yongin-si, KR;

Kwang-jin Moon, Hwaseong-si, KR;

Suk-Chul Bang, Yongin-si, KR;

Byung-Iyul Park, Seoul, KR;

Jeong-gi Jin, Osan-si, KR;

Tae-seong Kim, Suwon-si, KR;

Sung-hee Kang, Seongnam-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/40 (2006.01); H01L 23/48 (2006.01); H01L 23/485 (2006.01); H01L 23/50 (2006.01); H01L 21/768 (2006.01); H01L 23/498 (2006.01); H01L 25/065 (2006.01); H01L 25/18 (2006.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 21/76898 (2013.01); H01L 23/485 (2013.01); H01L 23/50 (2013.01); H01L 23/4985 (2013.01); H01L 23/49827 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 2224/16145 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/1437 (2013.01); H01L 2924/14511 (2013.01);
Abstract

Integrated circuit (IC) devices are provided including: a first multi-layer wiring structure including a plurality of first wiring layers in a first region of a substrate at different levels and spaced apart from one another, and a plurality of first contact plugs between the plurality of first wiring layers and connected to the plurality of first wiring layers; a through-silicon via (TSV) landing pad including a first pad layer in a second region of the substrate at a same level as that of at least one first wiring layer from among the plurality of first wiring layers, and a second pad layer at a same level as that of at least one first contact plug from among the plurality of first contact plugs and contacts the first pad layer; a second multi-layer wiring structure on the TSV landing pad; and a TSV structure that passes through the substrate and is connected to the second multi-layer wiring structure through the TSV landing pad.


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