The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 15, 2015

Filed:

Jun. 03, 2014
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Stefan Flachowsky, Dresden, DE;

Jan Hoentschel, Dresden, DE;

Gerd Zschaetzsch, Dresden, DE;

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 29/78 (2006.01); H01L 29/161 (2006.01); H01L 29/165 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/762 (2006.01); H01L 29/06 (2006.01); H01L 29/45 (2006.01); H01L 21/285 (2006.01); H01L 21/265 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823814 (2013.01); H01L 21/02532 (2013.01); H01L 21/26513 (2013.01); H01L 21/28518 (2013.01); H01L 21/76224 (2013.01); H01L 29/0653 (2013.01); H01L 29/161 (2013.01); H01L 29/165 (2013.01); H01L 29/456 (2013.01); H01L 29/665 (2013.01); H01L 29/6656 (2013.01); H01L 29/66636 (2013.01); H01L 29/7848 (2013.01);
Abstract

A method of forming a transistor device is provided, including the subsequently performed steps of forming a gate electrode on a first semiconductor layer, forming an interlayer dielectric over the gate electrode and the first semiconductor layer, forming a first opening in the interlayer dielectric at a predetermined distance laterally spaced from the gate electrode on one side of the gate electrode and a second opening in the interlayer dielectric at a predetermined distance laterally spaced from the gate electrode on another side of the gate electrode, the first and second openings reaching to the first semiconductor layer, forming cavities in the first semiconductor layer through the first and second openings formed in the interlayer dielectric, and forming embedded second semiconductor layers in the cavities.


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