The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 15, 2015
Filed:
Jun. 16, 2014
Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu, TW;
Chin-Hsiung Hsu, Guanyin Township, TW;
Huang-Yu Chen, Zhudong Township, TW;
Li-Chun Tien, Tainan, TW;
Lee-Chung Lu, Taipei, TW;
Hui-Zhong Zhuang, Kaohsiung, TW;
Cheng-I Huang, Hsinchu, TW;
Chung-Hsing Wang, Baoshan Township, TW;
Yi-Kan Cheng, Taipei, TW;
Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu, TW;
Abstract
Among other things, one or more techniques and/or systems for performing design layout are provided. In an example, a design layout corresponds to a layout of a standard cell whose connectivity is described by a netlist. For example, the netlist specifies net types for respective vias of the standard cell. One or more connectivity rings are formed within the design layout to provide connectivity for one or more vias of the design layout. For example, a first connectivity ring is generated, such as from mandrel, to connect one or more ring one vias. A second connectivity ring is generated, such as from passive pattern, to connect one or more ring two vias. One or more cuts are generated within the design layout to isolate vias having different net types. In this way, the design layout is self-aligned double patterning (SADP) compliant.