The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 08, 2015
Filed:
Mar. 29, 2012
Sheng-chen Chung, Jhubei, TW;
Ming Zhu, Singapore, SG;
Jyun-ming Lin, Hsinchu, TW;
Bao-ru Young, Zhubei, TW;
Hak-lay Chuang, Singapore, SG;
Sheng-Chen Chung, Jhubei, TW;
Ming Zhu, Singapore, SG;
Jyun-Ming Lin, Hsinchu, TW;
Bao-Ru Young, Zhubei, TW;
Hak-Lay Chuang, Singapore, SG;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
A method of semiconductor device fabrication including providing a substrate having a gate dielectric layer such as a high-k dielectric disposed thereon. A tri-layer element is formed on the gate dielectric layer. The tri-layer element includes a first capping layer, a second capping layer, and a metal gate layer interposing the first and second capping layer. One of an nFET and a pFET gate structure are formed using the tri-layer element, for example, the second capping layer and the metal gate layer may form a work function layer for one of an nFET and a pFET device. The first capping layer may be a sacrificial layer used to pattern the metal gate layer.