The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 08, 2015

Filed:

Mar. 31, 2014
Applicants:

Gregory S. Spencer, Hutto, TX (US);

Philip E. Crabtree, Austin, TX (US);

Dean J. Denning, Del Valle, TX (US);

Kurt H. Junker, Austin, TX (US);

Gerald A. Martin, Round Rock, TX (US);

Inventors:

Gregory S. Spencer, Hutto, TX (US);

Philip E. Crabtree, Austin, TX (US);

Dean J. Denning, Del Valle, TX (US);

Kurt H. Junker, Austin, TX (US);

Gerald A. Martin, Round Rock, TX (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 33/62 (2010.01); H01L 21/768 (2006.01); H01L 21/3105 (2006.01); H01L 23/00 (2006.01); H01L 23/488 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76879 (2013.01); H01L 21/31053 (2013.01); H01L 21/31056 (2013.01); H01L 21/76804 (2013.01); H01L 21/76885 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 2224/0345 (2013.01); H01L 2224/0362 (2013.01); H01L 2224/0391 (2013.01); H01L 2224/0392 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/05556 (2013.01); H01L 2224/05567 (2013.01); H01L 2224/05572 (2013.01); H01L 2224/05582 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05681 (2013.01); H01L 2224/05686 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/1305 (2013.01); H01L 2924/1461 (2013.01);
Abstract

A method for making a semiconductor device comprises forming an electrical interconnect layer, forming a first dielectric layer over the interconnect layer, forming an opening in the first dielectric layer over a first electrical interconnect of the interconnect layer, forming an aluminum layer over the first dielectric layer, etching the aluminum layer to form an aluminum die pad, forming a second dielectric layer over the aluminum die pad and the first dielectric layer, and forming a conductive via through the first and second dielectric layers to contact a second electrical interconnect of the interconnect layer.


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