The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 08, 2015
Filed:
Oct. 29, 2009
Applicants:
Beena Pious, Carrollton, TX (US);
Xiaowei Deng, Plano, TX (US);
Wah Kit Loh, Richardson, TX (US);
Jon Lescrenier, Dallas, TX (US);
Inventors:
Beena Pious, Carrollton, TX (US);
Xiaowei Deng, Plano, TX (US);
Wah Kit Loh, Richardson, TX (US);
Jon Lescrenier, Dallas, TX (US);
Assignee:
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G11C 29/12 (2006.01); G11C 29/02 (2006.01); G11C 11/22 (2006.01); G11C 11/41 (2006.01); G11C 29/50 (2006.01);
U.S. Cl.
CPC ...
G11C 29/842 (2013.01); G11C 29/02 (2013.01); G11C 29/025 (2013.01); G11C 29/12 (2013.01); G11C 11/22 (2013.01); G11C 11/41 (2013.01); G11C 2029/1204 (2013.01); G11C 2029/5006 (2013.01);
Abstract
An integrated circuit containing a memory and a sense amplifier. The integrated circuit also containing an extended delay circuit which extends the delay between when a precharged bitline is floated and when a wordline is enabled. A method of testing an integrated circuit to identify bitlines with excessive leakage.