The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 08, 2015
Filed:
Aug. 11, 2015
United Microelectronics Corp., Hsin-Chu, TW;
Po-Chao Tsao, New Taipei, TW;
Shih-Fang Hong, Tainan, TW;
Chia-Wei Huang, Kaohsiung, TW;
Ming-Jui Chen, Hsinchu, TW;
Shih-Fang Tzou, Tainan, TW;
Ming-Te Wei, Changhua County, TW;
UNITED MICROELECTRONICS CORP., Science-Based Industrial Park, Hsin-Chu, TW;
Abstract
A method of generating a layout pattern including a FinFET structure layout includes the following processes. First, a layout pattern, which includes a sub-pattern having pitches in simple integer ratios, is provided to a computer system. The sub-pattern is then classified into a first sub-pattern and a second sub-pattern. Afterwards, first stripe patterns and at least one second stripe pattern are generated. The longitudinal edges of the first stripe patterns are aligned with the longitudinal edges of the first sub-pattern and the first stripe patterns have equal spacings and widths. The positions of the second stripe patterns correspond to the positions of the blank pattern, and spacings or widths of the second stripe patterns are different from the spacings or widths of the first stripe patterns. Finally, the first stripe patterns and the second stripe pattern are outputted to a photomask.