The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 01, 2015
Filed:
Nov. 18, 2013
Applicants:
Chin Hock Toh, Singapore, SG;
Uday Mahajan, Singapore, SG;
Aksel Kitowski, Singapore, SG;
Inventors:
Assignee:
APPLIED MATERIALS, INC., Santa Clara, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
H01L 51/40 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 21/78 (2006.01); H01L 21/768 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 24/94 (2013.01); H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 21/6835 (2013.01); H01L 21/76898 (2013.01); H01L 21/78 (2013.01); H01L 23/481 (2013.01); H01L 21/6831 (2013.01); H01L 23/3128 (2013.01); H01L 2221/68327 (2013.01);
Abstract
Thin substrates and mold compound handling is described using an electrostatic-chucking carrier. In one example, a first part of a plurality of silicon chip packages is formed on a front side of a silicon substrate wafer at a first processing station. An a carrier wafer of an electrostatic chuck is attached over the front side of the silicon wafer. The substrate wafer is moved to a second processing station. A second part of the plurality of silicon chip packages are formed on a back side of the silicon wafer at a second processing station. The electrostatic chuck is then released.