The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 01, 2015
Filed:
May. 29, 2007
Applicant:
Jae Hak Yee, Singapore, SG;
Inventor:
Jae Hak Yee, Singapore, SG;
Assignee:
STATS ChipPAC Ltd., Singapore, SG;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/02 (2006.01); H01L 23/495 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 25/10 (2006.01); H01L 23/552 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49537 (2013.01); H01L 23/3121 (2013.01); H01L 23/3135 (2013.01); H01L 23/49575 (2013.01); H01L 24/73 (2013.01); H01L 25/0657 (2013.01); H01L 25/105 (2013.01); H01L 23/552 (2013.01); H01L 24/48 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/731 (2013.01); H01L 2224/73207 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06572 (2013.01); H01L 2225/1029 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01033 (2013.01); H01L 2924/01046 (2013.01); H01L 2924/01078 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/01082 (2013.01); H01L 2924/19107 (2013.01); H01L 2924/3025 (2013.01);
Abstract
A stackable multi-chip package system is provided including forming an inter-chip structure adjacent to an external interconnect having both a base and a tip; connecting a first integrated circuit die and an outer portion of the base with the first integrated circuit die mounted over the inter-chip structure, connecting a second integrated circuit die and an inner portion of the base with the second integrated circuit die mounted under the inter-chip structure, and molding the first integrated circuit die, the second integrated circuit die, and the external interconnect partially exposed.