The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 01, 2015
Filed:
Mar. 07, 2013
Applicant:
Kabushiki Kaisha Toshiba, Tokyo, JP;
Inventors:
Hideo Aoki, Kanagawa, JP;
Katsuhiko Oyama, Tokyo, JP;
Taku Nishiyama, Kanagawa, JP;
Chiaki Takubo, Tokyo, JP;
Katsuya Sakai, Kanagawa, JP;
Assignee:
Kabushiki Kaisha Toshiba, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 23/48 (2006.01); H01L 23/367 (2006.01); H01L 23/42 (2006.01); H01L 23/427 (2006.01); H01L 23/467 (2006.01);
U.S. Cl.
CPC ...
H01L 23/367 (2013.01); H01L 23/3677 (2013.01); H01L 23/42 (2013.01); H01L 23/427 (2013.01); H01L 23/467 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/73253 (2013.01); H01L 2924/15311 (2013.01);
Abstract
According to one embodiment, a semiconductor module has a substrate, two nonvolatile memories disposed on a first surface of the substrate, a controller to control the nonvolatile memories, disposed on the first surface of the substrate and between the two nonvolatile memories, and a plurality of terminals that are electrically connected to the two nonvolatile memories and to the controller, disposed on a second surface of the substrate.