The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 24, 2015

Filed:

Jan. 06, 2015
Applicant:

Kinsus Interconnect Technology Corp., Taoyuan, TW;

Inventors:

Ting-Hao Lin, Taipei, TW;

Yu-Te Lu, Taoyuan Hsien, TW;

Fu-Song Chen, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/18 (2006.01); H05K 1/03 (2006.01); H05K 1/11 (2006.01); H05K 1/02 (2006.01);
U.S. Cl.
CPC ...
H05K 1/183 (2013.01); H05K 1/0213 (2013.01); H05K 1/115 (2013.01); H05K 1/185 (2013.01); H05K 1/0298 (2013.01);
Abstract

A double sided board with buried element and a method for manufacturing the same are disclosed. At least one buried element is fixed on a dielectric layer and embedded in an insulation layer. First and second electrical circuits are formed on upper and lower surfaces of the insulation layer, respectively. At least one through-hole is formed in the insulation layer and filled with a conductive layer to electrically connect the first and the second electrical circuits. The dielectric layer beneath the buried element and the insulation layer above the buried element are provided with at least one opening, respectively, which is filled with the conductive layer, thereby connecting the conductive layer and external circuits or electrical elements. Additionally, the first and second electrical circuits are covered with first and second solder masks, respectively, so as to avoid environmental effect and improve preciseness of the circuits.


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