The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 24, 2015

Filed:

Jan. 18, 2012
Applicants:

Tsung-jen Liao, Hsinchu, TW;

Mei-fang Peng, Hsinchu, TW;

Cheng-tang Huang, Hsinchu, TW;

Inventors:

Tsung-Jen Liao, Hsinchu, TW;

Mei-Fang Peng, Hsinchu, TW;

Cheng-Tang Huang, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/60 (2006.01); H01L 23/13 (2006.01); H01L 23/498 (2006.01); H01L 25/10 (2006.01); H01L 21/683 (2006.01);
U.S. Cl.
CPC ...
H01L 23/13 (2013.01); H01L 21/6835 (2013.01); H01L 23/49816 (2013.01); H01L 23/49827 (2013.01); H01L 25/105 (2013.01); H01L 2221/68345 (2013.01); H01L 2221/68363 (2013.01); H01L 2224/16 (2013.01); H01L 2225/1041 (2013.01); H01L 2225/1058 (2013.01);
Abstract

A manufacturing method of semiconductor package structure includes: providing a first dielectric layer having multiple through holes; providing a second dielectric layer having multiple conductive vias and a chip-containing opening; laminating the second dielectric layer onto the first dielectric layer; disposing a chip in the chip-containing opening and adhering a rear surface of the chip onto the first dielectric layer exposed by the chip-containing opening; forming a redistribution circuit layer on the second dielectric layer wherein a part of the redistribution circuit layer extends from the second dielectric layer onto an active surface of the chip and the conductive vias so that the chip electrically connects the conductive vias through the partial redistribution circuit layer; forming multiple solder balls on the first dielectric layer wherein the solder balls are in the through holes and electrically connect the chip through the conductive vias and the redistribution circuit layer.


Find Patent Forward Citations

Liao, Tsung-Jen. (2015). Semiconductor package structure and manufacturing method thereof (U.S. Patent No. 9196553). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9196553

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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