The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 24, 2015
Filed:
Aug. 26, 2011
Applicants:
Chia-cheng Chou, Keelung, TW;
Chung-chi Ko, Nantou, TW;
Keng-chu Lin, Ping-Tung, TW;
Shwang-ming Jeng, Hsin-Chu, TW;
Inventors:
Chia-Cheng Chou, Keelung, TW;
Chung-Chi Ko, Nantou, TW;
Keng-Chu Lin, Ping-Tung, TW;
Shwang-Ming Jeng, Hsin-Chu, TW;
Assignee:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/66 (2006.01); H01L 21/3105 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 22/20 (2013.01); H01L 21/3105 (2013.01); H01L 21/31058 (2013.01); H01L 21/76814 (2013.01); H01L 21/76828 (2013.01); H01L 22/12 (2013.01);
Abstract
A method includes etching a low-k dielectric layer on a wafer to form an opening in the low-k dielectric layer. An amount of a detrimental substance in the wafer is measured to obtain a measurement result. Process conditions for baking the wafer are determined in response to the measurement result. The wafer is baked using the determined process conditions.