The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 24, 2015

Filed:

Sep. 10, 2012
Applicants:

Chieh-te Chen, Kaohsiung, TW;

Yi-po Lin, Tainan, TW;

Jiunn-hsiung Liao, Tainan, TW;

Feng-yi Chang, Tainan, TW;

Shang-yuan Tsai, Kaohsiung, TW;

Inventors:

Chieh-Te Chen, Kaohsiung, TW;

Yi-Po Lin, Tainan, TW;

Jiunn-Hsiung Liao, Tainan, TW;

Feng-Yi Chang, Tainan, TW;

Shang-Yuan Tsai, Kaohsiung, TW;

Assignee:

UNITED MICROELECTRONICS CORP., Science-Based Industrial Park, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 21/768 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76816 (2013.01); H01L 21/31144 (2013.01); H01L 21/76895 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A manufacturing method of a semiconductor device is disclosed in the present invention. First, at least one gate structure and plurality of source/drain regions on a substrate are formed, a dielectric layer is then formed on the substrate, a first contact hole and a second contact hole are formed in the dielectric layer, respectively on the gate structure and the source/drain region, and a third contact hole is formed in the dielectric layer, wherein the third contact hole overlaps the first contact hole and the second contact hole.


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