The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 17, 2015

Filed:

Dec. 12, 2014
Applicants:

Byoung-ho Kwon, Hwaseong-si, KR;

Cheol Kim, Hwaseong-si, KR;

Ho-young Kim, Seongnam-si, KR;

Se-jung Park, Hwaseong-si, KR;

Myeong-cheol Kim, Suwon-si, KR;

Bo-kyeong Kang, Seoul, KR;

Bo-un Yoon, Seoul, KR;

Jae-kwang Choi, Suwon-si, KR;

Si-young Choi, Seongnam-si, KR;

Suk-hoon Jeong, Suwon-si, KR;

Geum-jung Seong, Seoul, KR;

Hee-don Jeong, Hwaseong-si, KR;

Yong-joon Choi, Seoul, KR;

Ji-eun Han, Incheon, KR;

Inventors:

Byoung-Ho Kwon, Hwaseong-si, KR;

Cheol Kim, Hwaseong-si, KR;

Ho-Young Kim, Seongnam-si, KR;

Se-Jung Park, Hwaseong-si, KR;

Myeong-Cheol Kim, Suwon-si, KR;

Bo-Kyeong Kang, Seoul, KR;

Bo-Un Yoon, Seoul, KR;

Jae-Kwang Choi, Suwon-si, KR;

Si-Young Choi, Seongnam-si, KR;

Suk-Hoon Jeong, Suwon-si, KR;

Geum-Jung Seong, Seoul, KR;

Hee-Don Jeong, Hwaseong-si, KR;

Yong-Joon Choi, Seoul, KR;

Ji-Eun Han, Incheon, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/8238 (2006.01); H01L 21/8234 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0886 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 29/6656 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/49 (2013.01); H01L 29/78 (2013.01);
Abstract

Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.


Find Patent Forward Citations

Loading…