The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 17, 2015

Filed:

Oct. 02, 2014
Applicants:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Inventor:

Mieno Fumitake, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/265 (2006.01); H01L 21/8238 (2006.01); H01L 29/808 (2006.01); H01L 29/66 (2006.01); H01L 21/8232 (2006.01); H01L 27/098 (2006.01); H01L 27/12 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/43 (2006.01); H01L 21/266 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823821 (2013.01); H01L 21/265 (2013.01); H01L 21/266 (2013.01); H01L 21/8232 (2013.01); H01L 27/098 (2013.01); H01L 27/1211 (2013.01); H01L 29/0657 (2013.01); H01L 29/1037 (2013.01); H01L 29/1066 (2013.01); H01L 29/43 (2013.01); H01L 29/4916 (2013.01); H01L 29/6656 (2013.01); H01L 29/6681 (2013.01); H01L 29/66803 (2013.01); H01L 29/66901 (2013.01); H01L 29/808 (2013.01);
Abstract

A method of manufacturing a semiconductor device is provided. The method includes providing a fin protruding upwardly from or through a surface of a substrate, forming a to-be-sacrificed dummy gate enwrapping a first portion of the fin, forming a first insulating material layer so as to at least cover an exposed second portion of the fin, and selectively removing the dummy gate to thereby expose the first portion of the first semiconductor layer portion that was enwrapped by the dummy gate. The method further includes introducing, into the exposed portion of the first semiconductor layer portion, one or more dopants including a conductivity type reversing dopant, so as to form a channel region having a first conductivity type and at least two opposed channel control regions having a second conductivity type, wherein the channel control regions further comprise a portion formed above and adjoining a top of the channel region.


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