The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 17, 2015

Filed:

Jan. 21, 2014
Applicant:

Canon Anelva Corporation, Kawasaki-shi, JP;

Inventors:

Takashi Nakagawa, Hachioji, JP;

Masayoshi Ikeda, Hachioji, JP;

Yukito Nakagawa, Kokubunji, JP;

Yasushi Kamiya, Fuchu, JP;

Yoshimitsu Kodaira, Tama, JP;

Assignee:

Canon Anelva Corporation, Kawasaki-shi, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/302 (2006.01); H01L 21/3065 (2006.01); H01J 37/32 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/3065 (2013.01); H01J 37/32357 (2013.01); H01J 37/32403 (2013.01); H01J 37/32422 (2013.01); H01J 37/32458 (2013.01); H01J 37/32715 (2013.01); H01L 29/66795 (2013.01); H01L 29/66803 (2013.01);
Abstract

In fin FET fabrication, side walls of a semiconductor fin formed on a substrate have certain roughness. Using such fins having roughness may induce variations in characteristics between transistors due to their shapes or the like. An object of the present invention is to provide a fin FET fabrication method capable of improving device characteristic by easily reducing the roughness of the side walls of fins after formation. In one embodiment of the present invention, side walls of a semiconductor fin are etched by an ion beam extracted from a grid to reduce the roughness of the side walls.


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