The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 17, 2015

Filed:

Dec. 21, 2012
Applicants:

Jayashankar Bharadwaj, Saratoga, CA (US);

Nalini Vasudevan, Sunnyvale, CA (US);

Victor W. Lee, Santa Clara, CA (US);

Sara S. Baghsorkhi, San Jose, CA (US);

Albert Hartono, Santa Clara, CA (US);

Daehyun Kim, San Jose, CA (US);

Inventors:

Jayashankar Bharadwaj, Saratoga, CA (US);

Nalini Vasudevan, Sunnyvale, CA (US);

Victor W. Lee, Santa Clara, CA (US);

Sara S. Baghsorkhi, San Jose, CA (US);

Albert Hartono, Santa Clara, CA (US);

Daehyun Kim, San Jose, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 9/30 (2006.01); G06F 11/07 (2006.01);
U.S. Cl.
CPC ...
G06F 9/30145 (2013.01); G06F 11/073 (2013.01); G06F 11/0793 (2013.01);
Abstract

According to one embodiment, a processor includes an instruction decoder to decode an instruction to read a plurality of data elements from memory, the instruction having a first operand specifying a storage location, a second operand specifying a bitmask having one or more bits, each bit corresponding to one of the data elements, and a third operand specifying a memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the instruction, to read one or more data elements speculatively, based on the bitmask specified by the second operand, from a memory location based on the memory address indicated by the third operand, and to store the one or more data elements in the storage location indicated by the first operand.


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