The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2015

Filed:

Jan. 16, 2014
Applicants:

Intermolecular Inc., San Jose, CA (US);

Kabushiki Kaisha Toshiba, Tokyo, JP;

Sandisk 3d Llc, Milpitas, CA (US);

Inventors:

Yun Wang, San Jose, CA (US);

Tony P. Chiang, Campbell, CA (US);

Imran Hashim, Saratoga, CA (US);

Assignees:

Intermolecular, Inc., San Jose, CA (US);

Kabushiki Kaisha Toshiba, Tokyo, JP;

SanDisk 3D LLC, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 45/00 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
H01L 45/146 (2013.01); H01L 27/2409 (2013.01); H01L 27/2436 (2013.01); H01L 27/2463 (2013.01); H01L 45/065 (2013.01); H01L 45/08 (2013.01); H01L 45/10 (2013.01); H01L 45/12 (2013.01); H01L 45/1226 (2013.01); H01L 45/1233 (2013.01); H01L 45/1253 (2013.01); H01L 45/145 (2013.01); H01L 45/1608 (2013.01); H01L 45/1616 (2013.01); H01L 45/1625 (2013.01);
Abstract

Embodiments of the invention generally relate to a resistive switching nonvolatile memory device having an interface layer structure disposed between at least one of the electrodes and a variable resistance layer formed in the nonvolatile memory device, and a method of forming the same. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. In one configuration of the resistive switching nonvolatile memory device, the interface layer structure comprises a passivation region, an interface coupling region, and/or a variable resistance layer interface region that are configured to adjust the nonvolatile memory device's performance, such as lowering the formed device's switching currents and reducing the device's forming voltage, and reducing the performance variation from one formed device to another.


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