The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2015

Filed:

Oct. 05, 2012
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Brian M. Henderson, San Diego, CA (US);

Chiew-Guan Tan, San Diego, CA (US);

Gregory A. Uvieghara, San Diego, CA (US);

Reza Jalilizeinali, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02H 9/00 (2006.01); H01L 23/525 (2006.01); H01L 23/60 (2006.01); H01L 25/065 (2006.01); H01L 25/00 (2006.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5256 (2013.01); H01L 23/60 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 23/3128 (2013.01); H01L 23/481 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/73257 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06527 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06565 (2013.01);
Abstract

One feature pertains to a multi-chip module that comprises at least a first integrated circuit (IC) die and a second IC die. The second IC die has an input/output (I/O) node electrically coupled to the first IC die by a through substrate via. The second die's active surface also includes a fuse that is electrically coupled to the I/O node and adapted to protect the second IC die from damage caused by an electrostatic discharge (ESD). In particular, the fuse protects the second IC die from ESD that may be generated as a result of electrically coupling the first die to the second die during the manufacturing of the multi-chip module. Upon coupling the first die to the second die, the fuse may bypass the ESD current generated by the ESD to ground. After packaging of the multi-chip module is complete, the fuse may be blown open.


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