The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2015

Filed:

Jul. 31, 2013
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Szu-Lin Cheng, Yorktown Heights, NY (US);

Jack O. Chu, Manhasset Hills, NY (US);

Isaac Lauer, Yorktown Heights, NY (US);

Jeng-Bang Yau, Yorktown Heights, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 27/092 (2006.01); H01L 21/8238 (2006.01); H01L 27/12 (2006.01); H01L 21/84 (2006.01);
U.S. Cl.
CPC ...
H01L 27/092 (2013.01); H01L 21/823814 (2013.01); H01L 21/823871 (2013.01); H01L 21/84 (2013.01); H01L 27/1203 (2013.01);
Abstract

Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations and adjacent source/drain regions are defined on a semiconductor wafer, e.g., a silicon on insulator (SOI) wafer. Source/drains are formed in source/drains regions. A stopping layer is formed on source/drains. Contact spacers are formed above gates. Source/drain contacts are formed to the stopping layer, e.g., after converting the stopping layer to silicide. The contact spacers separate source/drain contacts from each other.


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