The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2015

Filed:

Mar. 08, 2013
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Chih-Tang Peng, Zhubei, TW;

Tai-Chung Huang, Hsin-Chu, TW;

Hao-Ming Lien, Hsin-Chu, TW;

Tze-Liang Lee, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 27/088 (2006.01); H01L 21/8238 (2006.01); H01L 27/108 (2006.01); H01L 21/762 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0886 (2013.01); H01L 21/76224 (2013.01); H01L 21/823431 (2013.01); H01L 21/823821 (2013.01); H01L 27/10879 (2013.01); H01L 29/7831 (2013.01);
Abstract

An isolation region gap fill method comprises depositing a first dielectric material over a semiconductor device through a flowable deposition process or other gap fill deposition processes, wherein the semiconductor device includes a first FinFET comprising a plurality of first fins and a second FinFET comprising a plurality of second fins. The method further comprises removing the first dielectric material between the first FinFET and the second FinFET to form an inter-device gap, depositing a second dielectric material into the inter-device gap and applying an annealing process to the semiconductor device.


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