The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 03, 2015
Filed:
Oct. 21, 2014
Applicant:
International Business Machines Corporation, Armonk, NY (US);
Inventors:
Daeik Kim, West Lafayette, IN (US);
Chandrasekharan Kothandaraman, Hopewell Junction, NY (US);
Chung-Hsun Lin, Hopewell Junction, NY (US);
John M. Safran, Wappingers Falls, NY (US);
Assignee:
International Business Machines Corporation, Armonk, NY (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 23/04 (2006.01); H01L 23/58 (2006.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/58 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 23/585 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 2224/0557 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/05684 (2013.01); H01L 2224/06181 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/1306 (2013.01); H01L 2924/3025 (2013.01); H01L 2924/3512 (2013.01);
Abstract
A semiconductor apparatus includes a substrate structure including a silicon substrate layer, a conductive through-substrate via extending through the silicon substrate layer. The apparatus further includes a semiconductor device located in the substrate structure and a conductive wall located between the through-substrate via and the semiconductor device. The conductive wall is in electrical contact with the silicon substrate layer.