The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2015

Filed:

Sep. 05, 2014
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Wei-Sheng Lei, San Jose, CA (US);

Brad Eaton, Menlo Park, CA (US);

Aparna Iyer, Sunnyvale, CA (US);

Todd Egan, Fremont, CA (US);

Madhava Rao Yalamanchili, Morgan Hill, CA (US);

Ajay Kumar, Cupertino, CA (US);

Assignee:

Applied Materials, Inc., Santa Clata, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/82 (2006.01); H01L 21/78 (2006.01); H01L 21/3065 (2006.01); H01L 21/308 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 21/82 (2013.01); H01L 21/308 (2013.01); H01L 21/3065 (2013.01); H01L 21/3081 (2013.01); H01L 21/31127 (2013.01); H01L 21/78 (2013.01);
Abstract

Methods of using a hybrid mask composed of a first water soluble film layer and a second water-soluble layer for wafer dicing using laser scribing and plasma etch described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a hybrid mask above the semiconductor wafer. The hybrid mask is composed of a first water-soluble layer disposed on the integrated circuits, and a second water-soluble layer disposed on the first water-soluble layer. The method also involves patterning the hybrid mask with a laser scribing process to provide a patterned hybrid mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The method also involves etching the semiconductor wafer through the gaps in the patterned hybrid mask to singulate the integrated circuits.


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