The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2015

Filed:

Aug. 11, 2014
Applicant:

Raytheon Company, Waltham, MA (US);

Inventors:

Roland Gooch, Dallas, TX (US);

Buu Diep, Murphy, TX (US);

Thomas Allan Kocian, Dallas, TX (US);

Stephen H. Black, Goleta, CA (US);

Adam M. Kennedy, Santa Barbara, CA (US);

Assignee:

RAYTHEON COMPANY, Waltham, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/12 (2006.01); B81B 7/00 (2006.01); B81C 1/00 (2006.01); H01L 23/053 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
B81B 7/0041 (2013.01); B81B 7/007 (2013.01); B81C 1/00269 (2013.01); H01L 23/053 (2013.01); H01L 24/83 (2013.01); B81C 2203/019 (2013.01); H01L 24/27 (2013.01); H01L 24/29 (2013.01); H01L 2224/27444 (2013.01); H01L 2224/27462 (2013.01); H01L 2224/27464 (2013.01); H01L 2224/291 (2013.01); H01L 2224/29011 (2013.01); H01L 2224/83001 (2013.01); H01L 2224/83007 (2013.01); H01L 2224/8314 (2013.01); H01L 2224/83139 (2013.01); H01L 2224/83141 (2013.01); H01L 2224/83192 (2013.01); H01L 2924/1461 (2013.01); H01L 2924/163 (2013.01);
Abstract

A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.


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