The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2015

Filed:

Dec. 19, 2011
Applicants:

Hans Krueger, Munich, DE;

Alexander Schmajew, Munich, DE;

Alois Stelzl, Munich, DE;

Inventors:

Hans Krueger, Munich, DE;

Alexander Schmajew, Munich, DE;

Alois Stelzl, Munich, DE;

Assignee:

EPCOS AG, Munich, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 3/02 (2006.01); H05K 3/10 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 25/00 (2006.01); B81B 7/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/94 (2013.01); B81B 7/007 (2013.01); H01L 24/24 (2013.01); H01L 24/82 (2013.01); H01L 24/97 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); B81B 2207/098 (2013.01); H01L 2224/24011 (2013.01); H01L 2224/24051 (2013.01); H01L 2224/24147 (2013.01); H01L 2224/24991 (2013.01); H01L 2224/94 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06551 (2013.01); H01L 2924/014 (2013.01); H01L 2924/01005 (2013.01); H01L 2924/01006 (2013.01); H01L 2924/01033 (2013.01); H01L 2924/01047 (2013.01); H01L 2924/01068 (2013.01); H01L 2924/01082 (2013.01); H01L 2924/1068 (2013.01); H01L 2924/14 (2013.01); H01L 2924/1461 (2013.01); Y10T 29/49126 (2015.01);
Abstract

A plurality of unpackaged substrates connected to one another is disclosed. The stepped structures on and/or in a first main area of a first substrate include a plurality of integrated circuits. The stepped structures run between the integrated circuits. The first conductor tracks extend from at least some contact connections of the respective integrated circuits as far as the stepped structures. The first substrate is connected on the side of the first main area to a further substrate. The first substrate is severed from a second main area opposite to the first main area such that the first substrate is divided into a plurality of substrate pieces. Each substrate piece has one of the integrated circuits. The first conductor tracks are accessible in interspaces between the substrate pieces. The second conductor tracks are formed from the second main area. At least some of the second conductor tracks lead from the second main area over side walls of the substrate pieces as far as the first conductor tracks.


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