The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 20, 2015
Filed:
Dec. 22, 2014
Applicant:
Globalfoundries Inc., Grand Cayman, KY;
Inventors:
Assignee:
GLOBALFOUNDRIES Inc., Grand Cayman, KY;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/84 (2006.01); H01L 21/02 (2006.01); H01L 21/8238 (2006.01); H01L 21/762 (2006.01); H01L 29/66 (2006.01); H01L 27/12 (2006.01); H01L 27/06 (2006.01); H01L 21/8234 (2006.01); H01L 29/94 (2006.01); H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
H01L 21/84 (2013.01); H01L 21/02428 (2013.01); H01L 21/76283 (2013.01); H01L 21/823412 (2013.01); H01L 21/823878 (2013.01); H01L 27/0629 (2013.01); H01L 27/1207 (2013.01); H01L 29/66181 (2013.01); H01L 27/088 (2013.01); H01L 29/945 (2013.01);
Abstract
A structure comprises a semiconductor substrate, a semiconductor-on-insulator region and a bulk region. The semiconductor-on-insulator region comprises a first semiconductor region, a dielectric layer provided between the semiconductor substrate and the first semiconductor region, and a first transistor comprising an active region provided in the first semiconductor region. The dielectric layer provides electrical isolation between the first semiconductor region and the semiconductor substrate. The bulk region comprises a second semiconductor region provided directly on the semiconductor substrate.