The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2015

Filed:

May. 27, 2014
Applicant:

United Microelectronics Corp., Hsinchu, TW;

Inventors:

Po-Hua Chen, Changhua County, TW;

Yu-Yee Liow, Hsinchu County, TW;

Wen-Hong Hsu, Hsinchu, TW;

Hsueh-Chen Cheng, Hsinchu County, TW;

Ya-Nan Mou, Hsinchu, TW;

Yuan-Hui Chen, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01); H03L 7/099 (2006.01); H03L 7/08 (2006.01); H03L 7/085 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0992 (2013.01); H03L 7/0802 (2013.01); H03L 7/085 (2013.01);
Abstract

A phase-locked loop (PLL) and a method for controlling the PLL are provided. The PLL includes a phase detector, a charge pump, a voltage-controlled oscillator (VCO), a feedback frequency divider, and a detector circuit. The phase detector generates a direction signal according to a comparison between phases of a first clock signal and a second clock signal. The charge pump converts the direction signal into a control voltage. The VCO generates a third clock signal. The control voltage controls a frequency of the third clock signal. The feedback frequency divider divides the frequency of the third clock signal to generate the second clock signal. The detector circuit sends a pulse signal to restart the VCO when the control voltage conforms to a preset condition.


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