The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9159723 B1

PDF
Full Text
Expired
Date of Patent:
Oct. 13, 2015

Filed:

Sep. 16, 2013
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chung-Yen Chou, Hsinchu, TW;

Po-Ken Lin, Hsinchu, TW;

Chia-Shiung Tsai, Hsin-Chu, TW;

Xiao-Meng Chen, Hsinchu County, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 49/02 (2006.01); H01L 27/08 (2006.01); H01L 29/66 (2006.01); H01L 29/94 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0805 (2013.01); H01L 28/90 (2013.01); H01L 29/66181 (2013.01); H01L 29/945 (2013.01);
Abstract

A novel method for manufacturing a semiconductor device and a semiconductor device are provided. The semiconductor device includes a substrate, a trench capacitor, a contact pad, an inter-layer dielectric (ILD) layer and contact elements. The trench capacitor includes a doped region, a first dielectric layer, a bottom electrode, a second dielectric layer and a top electrode, in which the contact pad is positioned on the doped region. The ILD layer has contact windows, and the contact elements are disposed therein. Because of the presence of the contact pad positioned on the doped region, the thickness of the ILD layer over the top electrode is increased but still satisfying the requirement of the maximum depth limit to the contact windows of etching the ILD layer.


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