The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 13, 2015
Filed:
Jan. 05, 2015
Wei-sheng Lei, San Jose, CA (US);
Prabhat Kumar, Fremont, CA (US);
James S. Papanu, San Rafael, CA (US);
Brad Eaton, Menlo Park, CA (US);
Ajay Kumar, Cupertino, CA (US);
Wei-Sheng Lei, San Jose, CA (US);
Prabhat Kumar, Fremont, CA (US);
James S. Papanu, San Rafael, CA (US);
Brad Eaton, Menlo Park, CA (US);
Ajay Kumar, Cupertino, CA (US);
Applied Materials, Inc., Santa Clara, CA (US);
Abstract
Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves laminating a polymeric mask layer onto a front side of the semiconductor wafer by dry film vacuum lamination, the polymeric mask layer covering and protecting the integrated circuits. The method also involves patterning the polymeric mask layer with a laser scribing process to provide gaps in the polymeric mask layer, the gaps exposing regions of the semiconductor wafer between the integrated circuits. The method also involves plasma etching the semiconductor wafer through the gaps in the polymeric mask layer to singulate the integrated circuits. The method also involves, subsequent to plasma etching the semiconductor wafer, removing the polymeric mask layer.