The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2015

Filed:

Oct. 30, 2008
Applicants:

Hui Ouyang, Chubei, TW;

Jean-luc Everaert, Gooik, BE;

Laura Nyns, Geetbets, BE;

Rita Vos, Tremelo, BE;

Inventors:

Hui OuYang, Chubei, TW;

Jean-Luc Everaert, Gooik, BE;

Laura Nyns, Geetbets, BE;

Rita Vos, Tremelo, BE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/314 (2006.01); H01L 21/02 (2006.01); H01L 21/316 (2006.01); H01L 21/28 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 21/3141 (2013.01); H01L 21/02057 (2013.01); H01L 21/28194 (2013.01); H01L 21/28211 (2013.01); H01L 21/31645 (2013.01); H01L 21/31654 (2013.01); H01L 29/517 (2013.01); H01L 21/28167 (2013.01); H01L 29/513 (2013.01);
Abstract

The present disclosure relates to methods for forming a high-k gate dielectric, the methods comprising the steps of providing a semiconductor substrate, cleaning the substrate, performing a thermal treatment, and performing a high-k dielectric material deposition, wherein said thermal treatment step is performed in a non-oxidizing ambient, leading to the formation of a thin interfacial layer between said semiconductor substrate and said high-k dielectric material and wherein the thickness of said thin interfacial layer is less than 10 Å.


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