The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2015

Filed:

Feb. 28, 2012
Applicants:

Da-wei Lai, Singapore, SG;

Mahadeva Iyer Natarajan, Clifton Park, NY (US);

Inventors:

Da-Wei Lai, Singapore, SG;

Mahadeva Iyer Natarajan, Clifton Park, NY (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 17/082 (2006.01); H01L 23/62 (2006.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
H03K 17/082 (2013.01); H01L 23/62 (2013.01); H01L 27/0921 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A device is presented. The device includes a first circuit coupled to first and second power rails of the device. The first circuit is subject to a latch up event in the presence of a latch up condition. The latch up event includes a low resistance path created between the first and second power rails. The device also includes a latch up sensing (LUS) circuit coupled to the first circuit. The LUS circuit is configured to receive a LUS input signal from the first circuit and generates a LUS output signal to the first circuit. When the input signal is an active latch up signal which indicates the presence of a latch up condition, the LUS circuit generates an active LUS output signal which creates a break in the low resistance path to terminate the latch up event.


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